Dynamic random access (DRAM) modules such as double data rate (DDR) synchronous dynamic random-access memories (SRAMs) use a synchronous communications protocol (i.e., DDR protocol). A memory controller is responsible for the synchronous timing, control, and data movement to and from the DRAM. In that regards, the DRAM is a slave device and DRAM provides only limited feedback to the memory controller.
Future memory interfaces may be transactional interfaces. Transactional interfaces can support both non-volatile and volatile memories co-located on a memory channel as a main memory. However, transactional interfaces involve variable timings, and much more feedback is expected from a memory-channel device. Therefore, there is a need for a transaction-based asynchronous communication protocol to support a memory module including non-volatile memories or both non-volatile and volatile memories that can provide device feedback to a memory controller.